Project Information                                        w:\odin\hat\hat.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 11/11/2002 13:35:52

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

hat       EPM7064LC44-7    1        21       0      33      13          51 %

User Pins:                 1        21       0  



Project Information                                        w:\odin\hat\hat.rpt

** FILE HIERARCHY **



|74192:1|
|74192:4|
|74192:6|
|7447:3|
|7447:5|
|7446:31|


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

***** Logic for device 'hat' compiled without errors.




Device: EPM7064LC44-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

                                           h  h  
                                           u  u  
                R  R  R                    n  n  
                E  E  E                    d  d  
                S  S  S                    r  r  
                E  E  E                    e  e  
                R  R  R                    d  d  
                V  V  V  V  G  G  G  G  G  s  s  
                E  E  E  C  N  N  N  N  N  _  _  
                D  D  D  C  D  D  D  D  D  e  f  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
  RESERVED |  7                                39 | hundreds_a 
  RESERVED |  8                                38 | hundreds_g 
  RESERVED |  9                                37 | tens_d 
       GND | 10                                36 | hundreds_b 
  RESERVED | 11                                35 | VCC 
     clock | 12         EPM7064LC44-7          34 | hundreds_c 
  RESERVED | 13                                33 | hundreds_d 
  RESERVED | 14                                32 | ones_c 
       VCC | 15                                31 | ones_b 
    tens_g | 16                                30 | GND 
    tens_f | 17                                29 | RESERVED 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                t  t  t  t  G  V  o  o  o  o  o  
                e  e  e  e  N  C  n  n  n  n  n  
                n  n  n  n  D  C  e  e  e  e  e  
                s  s  s  s        s  s  s  s  s  
                _  _  _  _        _  _  _  _  _  
                e  c  b  a        d  g  f  e  a  
                                                 
                                                 
                                                 
                                                 


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     6/16( 37%)   6/ 8( 75%)   0/16(  0%)   4/36( 11%) 
C:    LC33 - LC48    11/16( 68%)   7/ 8( 87%)   4/16( 25%)   5/36( 13%) 
D:    LC49 - LC64    16/16(100%)   8/ 8(100%)   9/16( 56%)  11/36( 30%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            22/32     ( 68%)
Total logic cells used:                         33/64     ( 51%)
Total shareable expanders used:                 13/64     ( 20%)
Total Turbo logic cells used:                   33/64     ( 51%)
Total shareable expanders not available (n/a):   0/64     (  0%)
Average fan-in:                                  4.45
Total fan-in:                                   147

Total input pins required:                       1
Total output pins required:                     21
Total bidirectional pins required:               0
Total logic cells required:                     33
Total flipflops required:                       12
Total product terms required:                   91
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          12

Synthesized logic cells:                         0/  64   (  0%)



Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  12    (1)  (A)      INPUT               0      0   0    0    0    0   12  clock


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     57    D     OUTPUT      t        0      0   0    0    4    0    0  hundreds_a
  36     52    D     OUTPUT      t        0      0   0    0    4    0    0  hundreds_b
  34     51    D     OUTPUT      t        0      0   0    0    4    0    0  hundreds_c
  33     49    D     OUTPUT      t        0      0   0    0    3    0    0  hundreds_d
  41     64    D     OUTPUT      t        0      0   0    0    3    0    0  hundreds_e
  40     62    D     OUTPUT      t        0      0   0    0    4    0    0  hundreds_f
  38     56    D     OUTPUT      t        0      0   0    0    4    0    0  hundreds_g
  28     40    C     OUTPUT      t        0      0   0    0    4    0    0  ones_a
  31     46    C     OUTPUT      t        0      0   0    0    4    0    0  ones_b
  32     48    C     OUTPUT      t        0      0   0    0    4    0    0  ones_c
  24     33    C     OUTPUT      t        0      0   0    0    3    0    0  ones_d
  27     37    C     OUTPUT      t        0      0   0    0    3    0    0  ones_e
  26     36    C     OUTPUT      t        0      0   0    0    4    0    0  ones_f
  25     35    C     OUTPUT      t        0      0   0    0    4    0    0  ones_g
  21     17    B     OUTPUT      t        0      0   0    0    4    0    0  tens_a
  20     19    B     OUTPUT      t        0      0   0    0    4    0    0  tens_b
  19     20    B     OUTPUT      t        0      0   0    0    4    0    0  tens_c
  37     53    D     OUTPUT      t        0      0   0    0    3    0    0  tens_d
  18     21    B     OUTPUT      t        0      0   0    0    3    0    0  tens_e
  17     24    B     OUTPUT      t        0      0   0    0    4    0    0  tens_f
  16     25    B     OUTPUT      t        0      0   0    0    4    0    0  tens_g


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     38    C       TFFE      t        2      1   0    1    4    5   10  |74192:1|QD (|74192:1|:23)
 (29)    41    C       TFFE      t        1      0   0    1    2    7    1  |74192:1|QC (|74192:1|:24)
   -     42    C       TFFE      t        1      0   0    1    2    7    2  |74192:1|QB (|74192:1|:25)
   -     34    C       TFFE      t        0      0   0    1    0    7   11  |74192:1|QA (|74192:1|:26)
   -     54    D       TFFE      t        2      1   0    1    6    5    6  |74192:4|QD (|74192:4|:23)
   -     50    D       TFFE      t        1      0   0    1    4    7    1  |74192:4|QC (|74192:4|:24)
   -     55    D       TFFE      t        1      0   0    1    4    7    2  |74192:4|QB (|74192:4|:25)
   -     61    D       TFFE      t        1      1   0    1    2    7    7  |74192:4|QA (|74192:4|:26)
   -     63    D       TFFE      t        2      0   0    1    8    5    2  |74192:6|QD (|74192:6|:23)
   -     58    D       TFFE      t        1      0   0    1    6    7    1  |74192:6|QC (|74192:6|:24)
   -     59    D       TFFE      t        1      0   0    1    6    7    2  |74192:6|QB (|74192:6|:25)
   -     60    D       TFFE      t        1      1   0    1    4    7    3  |74192:6|QA (|74192:6|:26)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                     Logic cells placed in LAB 'B'
        +----------- LC17 tens_a
        | +--------- LC19 tens_b
        | | +------- LC20 tens_c
        | | | +----- LC21 tens_e
        | | | | +--- LC24 tens_f
        | | | | | +- LC25 tens_g
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'B'
LC      | | | | | | | A B C D |     Logic cells that feed LAB 'B':

Pin
LC54 -> * * * - * * | - * - * | <-- |74192:4|QD
LC50 -> * * * * * * | - * - * | <-- |74192:4|QC
LC55 -> * * * * * * | - * - * | <-- |74192:4|QB
LC61 -> * * * * * * | - * - * | <-- |74192:4|QA


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                               Logic cells placed in LAB 'C'
        +--------------------- LC40 ones_a
        | +------------------- LC46 ones_b
        | | +----------------- LC48 ones_c
        | | | +--------------- LC33 ones_d
        | | | | +------------- LC37 ones_e
        | | | | | +----------- LC36 ones_f
        | | | | | | +--------- LC35 ones_g
        | | | | | | | +------- LC38 |74192:1|QD
        | | | | | | | | +----- LC41 |74192:1|QC
        | | | | | | | | | +--- LC42 |74192:1|QB
        | | | | | | | | | | +- LC34 |74192:1|QA
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC38 -> * * * - - * * * - * - | - - * * | <-- |74192:1|QD
LC41 -> * * * * * * * * * - - | - - * - | <-- |74192:1|QC
LC42 -> * * * * * * * * * * - | - - * - | <-- |74192:1|QB
LC34 -> * * * * * * * * * * * | - - * * | <-- |74192:1|QA

Pin
12   -> - - - - - - - * * * * | - - * * | <-- clock


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC57 hundreds_a
        | +----------------------------- LC52 hundreds_b
        | | +--------------------------- LC51 hundreds_c
        | | | +------------------------- LC49 hundreds_d
        | | | | +----------------------- LC64 hundreds_e
        | | | | | +--------------------- LC62 hundreds_f
        | | | | | | +------------------- LC56 hundreds_g
        | | | | | | | +----------------- LC53 tens_d
        | | | | | | | | +--------------- LC54 |74192:4|QD
        | | | | | | | | | +------------- LC50 |74192:4|QC
        | | | | | | | | | | +----------- LC55 |74192:4|QB
        | | | | | | | | | | | +--------- LC61 |74192:4|QA
        | | | | | | | | | | | | +------- LC63 |74192:6|QD
        | | | | | | | | | | | | | +----- LC58 |74192:6|QC
        | | | | | | | | | | | | | | +--- LC59 |74192:6|QB
        | | | | | | | | | | | | | | | +- LC60 |74192:6|QA
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC54 -> - - - - - - - - * - * - * * * * | - * - * | <-- |74192:4|QD
LC50 -> - - - - - - - * * * - - - - - - | - * - * | <-- |74192:4|QC
LC55 -> - - - - - - - * * * * - - - - - | - * - * | <-- |74192:4|QB
LC61 -> - - - - - - - * * * * * * * * * | - * - * | <-- |74192:4|QA
LC63 -> * * * - - * * - - - - - * - * - | - - - * | <-- |74192:6|QD
LC58 -> * * * * * * * - - - - - * * - - | - - - * | <-- |74192:6|QC
LC59 -> * * * * * * * - - - - - * * * - | - - - * | <-- |74192:6|QB
LC60 -> * * * * * * * - - - - - * * * * | - - - * | <-- |74192:6|QA

Pin
12   -> - - - - - - - - * * * * * * * * | - - * * | <-- clock
LC38 -> - - - - - - - - * * * * * * * * | - - * * | <-- |74192:1|QD
LC34 -> - - - - - - - - * * * * * * * * | - - * * | <-- |74192:1|QA


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               w:\odin\hat\hat.rpt
hat

** EQUATIONS **

clock    : INPUT;

-- Node name is 'hundreds_a' 
-- Equation name is 'hundreds_a', location is LC057, type is output.
 hundreds_a = LCELL( _EQ001 $  GND);
  _EQ001 = !_LC058 & !_LC059 &  _LC060 & !_LC063
         #  _LC059 &  _LC063
         #  _LC058 & !_LC060;

-- Node name is 'hundreds_b' 
-- Equation name is 'hundreds_b', location is LC052, type is output.
 hundreds_b = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC058 &  _LC059 & !_LC060
         #  _LC058 & !_LC059 &  _LC060
         #  _LC059 &  _LC063;

-- Node name is 'hundreds_c' 
-- Equation name is 'hundreds_c', location is LC051, type is output.
 hundreds_c = LCELL( _EQ003 $  GND);
  _EQ003 = !_LC058 &  _LC059 & !_LC060
         #  _LC058 &  _LC063;

-- Node name is 'hundreds_d' 
-- Equation name is 'hundreds_d', location is LC049, type is output.
 hundreds_d = LCELL( _EQ004 $  _LC060);
  _EQ004 = !_LC058 &  _LC059 &  _LC060
         #  _LC058 & !_LC059;

-- Node name is 'hundreds_e' 
-- Equation name is 'hundreds_e', location is LC064, type is output.
 hundreds_e = LCELL( _EQ005 $  _LC060);
  _EQ005 =  _LC058 & !_LC059 & !_LC060;

-- Node name is 'hundreds_f' 
-- Equation name is 'hundreds_f', location is LC062, type is output.
 hundreds_f = LCELL( _EQ006 $  _LC059);
  _EQ006 = !_LC058 & !_LC059 &  _LC060 & !_LC063
         #  _LC058 &  _LC059 & !_LC060;

-- Node name is 'hundreds_g' 
-- Equation name is 'hundreds_g', location is LC056, type is output.
 hundreds_g = LCELL( _EQ007 $  GND);
  _EQ007 =  _LC058 &  _LC059 &  _LC060
         # !_LC058 & !_LC059 & !_LC063;

-- Node name is 'ones_a' 
-- Equation name is 'ones_a', location is LC040, type is output.
 ones_a  = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC034 & !_LC038 & !_LC041 & !_LC042
         #  _LC038 &  _LC042
         # !_LC034 &  _LC041;

-- Node name is 'ones_b' 
-- Equation name is 'ones_b', location is LC046, type is output.
 ones_b  = LCELL( _EQ009 $  GND);
  _EQ009 = !_LC034 &  _LC041 &  _LC042
         #  _LC034 &  _LC041 & !_LC042
         #  _LC038 &  _LC042;

-- Node name is 'ones_c' 
-- Equation name is 'ones_c', location is LC048, type is output.
 ones_c  = LCELL( _EQ010 $  GND);
  _EQ010 = !_LC034 & !_LC041 &  _LC042
         #  _LC038 &  _LC041;

-- Node name is 'ones_d' 
-- Equation name is 'ones_d', location is LC033, type is output.
 ones_d  = LCELL( _EQ011 $  _LC034);
  _EQ011 =  _LC034 & !_LC041 &  _LC042
         #  _LC041 & !_LC042;

-- Node name is 'ones_e' 
-- Equation name is 'ones_e', location is LC037, type is output.
 ones_e  = LCELL( _EQ012 $  _LC034);
  _EQ012 = !_LC034 &  _LC041 & !_LC042;

-- Node name is 'ones_f' 
-- Equation name is 'ones_f', location is LC036, type is output.
 ones_f  = LCELL( _EQ013 $  _LC042);
  _EQ013 =  _LC034 & !_LC038 & !_LC041 & !_LC042
         # !_LC034 &  _LC041 &  _LC042;

-- Node name is 'ones_g' 
-- Equation name is 'ones_g', location is LC035, type is output.
 ones_g  = LCELL( _EQ014 $  GND);
  _EQ014 =  _LC034 &  _LC041 &  _LC042
         # !_LC038 & !_LC041 & !_LC042;

-- Node name is 'tens_a' 
-- Equation name is 'tens_a', location is LC017, type is output.
 tens_a  = LCELL( _EQ015 $  GND);
  _EQ015 = !_LC050 & !_LC054 & !_LC055 &  _LC061
         #  _LC054 &  _LC055
         #  _LC050 & !_LC061;

-- Node name is 'tens_b' 
-- Equation name is 'tens_b', location is LC019, type is output.
 tens_b  = LCELL( _EQ016 $  GND);
  _EQ016 =  _LC050 &  _LC055 & !_LC061
         #  _LC050 & !_LC055 &  _LC061
         #  _LC054 &  _LC055;

-- Node name is 'tens_c' 
-- Equation name is 'tens_c', location is LC020, type is output.
 tens_c  = LCELL( _EQ017 $  GND);
  _EQ017 = !_LC050 &  _LC055 & !_LC061
         #  _LC050 &  _LC054;

-- Node name is 'tens_d' 
-- Equation name is 'tens_d', location is LC053, type is output.
 tens_d  = LCELL( _EQ018 $  _LC061);
  _EQ018 = !_LC050 &  _LC055 &  _LC061
         #  _LC050 & !_LC055;

-- Node name is 'tens_e' 
-- Equation name is 'tens_e', location is LC021, type is output.
 tens_e  = LCELL( _EQ019 $  _LC061);
  _EQ019 =  _LC050 & !_LC055 & !_LC061;

-- Node name is 'tens_f' 
-- Equation name is 'tens_f', location is LC024, type is output.
 tens_f  = LCELL( _EQ020 $  _LC055);
  _EQ020 = !_LC050 & !_LC054 & !_LC055 &  _LC061
         #  _LC050 &  _LC055 & !_LC061;

-- Node name is 'tens_g' 
-- Equation name is 'tens_g', location is LC025, type is output.
 tens_g  = LCELL( _EQ021 $  GND);
  _EQ021 =  _LC050 &  _LC055 &  _LC061
         # !_LC050 & !_LC054 & !_LC055;

-- Node name is '|74192:1|:26' = '|74192:1|QA' 
-- Equation name is '_LC034', type is buried 
_LC034   = TFFE( VCC,  clock,  VCC,  VCC,  VCC);

-- Node name is '|74192:1|:25' = '|74192:1|QB' 
-- Equation name is '_LC042', type is buried 
_LC042   = TFFE( VCC,  _EQ022,  VCC,  VCC,  VCC);
  _EQ022 =  _X001;
  _X001  = EXP(!clock &  _LC034 & !_LC038);

-- Node name is '|74192:1|:24' = '|74192:1|QC' 
-- Equation name is '_LC041', type is buried 
_LC041   = TFFE( VCC,  _EQ023,  VCC,  VCC,  VCC);
  _EQ023 =  _X002;
  _X002  = EXP(!clock &  _LC034 &  _LC042);

-- Node name is '|74192:1|:23' = '|74192:1|QD' 
-- Equation name is '_LC038', type is buried 
_LC038   = TFFE( VCC,  _EQ024,  VCC,  VCC,  VCC);
  _EQ024 =  _X003 &  _X004;
  _X003  = EXP(!clock &  _LC034 &  _LC038);
  _X004  = EXP(!clock &  _LC034 &  _LC041 &  _LC042);

-- Node name is '|74192:4|:26' = '|74192:4|QA' 
-- Equation name is '_LC061', type is buried 
_LC061   = TFFE( VCC,  _EQ025,  VCC,  VCC,  VCC);
  _EQ025 =  _X003;
  _X003  = EXP(!clock &  _LC034 &  _LC038);

-- Node name is '|74192:4|:25' = '|74192:4|QB' 
-- Equation name is '_LC055', type is buried 
_LC055   = TFFE( VCC,  _EQ026,  VCC,  VCC,  VCC);
  _EQ026 =  _X005;
  _X005  = EXP(!clock &  _LC034 &  _LC038 & !_LC054 &  _LC061);

-- Node name is '|74192:4|:24' = '|74192:4|QC' 
-- Equation name is '_LC050', type is buried 
_LC050   = TFFE( VCC,  _EQ027,  VCC,  VCC,  VCC);
  _EQ027 =  _X006;
  _X006  = EXP(!clock &  _LC034 &  _LC038 &  _LC055 &  _LC061);

-- Node name is '|74192:4|:23' = '|74192:4|QD' 
-- Equation name is '_LC054', type is buried 
_LC054   = TFFE( VCC,  _EQ028,  VCC,  VCC,  VCC);
  _EQ028 =  _X007 &  _X008;
  _X007  = EXP(!clock &  _LC034 &  _LC038 &  _LC050 &  _LC055 &  _LC061);
  _X008  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC061);

-- Node name is '|74192:6|:26' = '|74192:6|QA' 
-- Equation name is '_LC060', type is buried 
_LC060   = TFFE( VCC,  _EQ029,  VCC,  VCC,  VCC);
  _EQ029 =  _X008;
  _X008  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC061);

-- Node name is '|74192:6|:25' = '|74192:6|QB' 
-- Equation name is '_LC059', type is buried 
_LC059   = TFFE( VCC,  _EQ030,  VCC,  VCC,  VCC);
  _EQ030 =  _X009;
  _X009  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC060 &  _LC061 & !_LC063);

-- Node name is '|74192:6|:24' = '|74192:6|QC' 
-- Equation name is '_LC058', type is buried 
_LC058   = TFFE( VCC,  _EQ031,  VCC,  VCC,  VCC);
  _EQ031 =  _X010;
  _X010  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC059 &  _LC060 &  _LC061);

-- Node name is '|74192:6|:23' = '|74192:6|QD' 
-- Equation name is '_LC063', type is buried 
_LC063   = TFFE( VCC,  _EQ032,  VCC,  VCC,  VCC);
  _EQ032 =  _X011 &  _X012;
  _X011  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC060 &  _LC061 &  _LC063);
  _X012  = EXP(!clock &  _LC034 &  _LC038 &  _LC054 &  _LC058 &  _LC059 &  _LC060 & 
              _LC061);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X003 occurs in LABs C, D




Project Information                                        w:\odin\hat\hat.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,839K
